作业帮object "process_en" on left-hand side of assignment must hav
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object "process_en" on left-hand side of assignment must have a net type
我用qusrturs 进行verilog语言编写一个顶层文件时候老是出现上面这个问题,具体程序段如下
module fifo_top(wr,data,clk,q,ready,process_en);
input wr,clk;
input[7:0] data;
output ready,process_en;
output[7:0] q;
reg ready,process_en;
wire rd1,f1,e1,w1,co1;
assign rd1=ready;
assign process_en=~rd1;
assign w1=wr&process_en;
counter2 counter2(
.clk(clk),
.co(co1)
);
fifoo1 fifoo1(
.WE(w1),
.RE(rd1),
.WCLOCK(clk),
.RCLOCK(co),
.DATA(data),
.Q(q),
.FULL(f1),
.EMPTY(e1),
.AFULL(),
.AEMPTY()
);
df df(
.clr(e1),
.d(),
.clk(f1),
.q(rd1)
);
endmodule
我用qusrturs 进行verilog语言编写一个顶层文件时候老是出现上面这个问题,具体程序段如下
module fifo_top(wr,data,clk,q,ready,process_en);
input wr,clk;
input[7:0] data;
output ready,process_en;
output[7:0] q;
reg ready,process_en;
wire rd1,f1,e1,w1,co1;
assign rd1=ready;
assign process_en=~rd1;
assign w1=wr&process_en;
counter2 counter2(
.clk(clk),
.co(co1)
);
fifoo1 fifoo1(
.WE(w1),
.RE(rd1),
.WCLOCK(clk),
.RCLOCK(co),
.DATA(data),
.Q(q),
.FULL(f1),
.EMPTY(e1),
.AFULL(),
.AEMPTY()
);
df df(
.clr(e1),
.d(),
.clk(f1),
.q(rd1)
);
endmodule
简单 reg ready,process_en; 改为
reg ready；
wire process_en;
reg ready；
wire process_en;
object "process_en" on left-hand side of assignment must hav
new Address[]()那里报The left-hand side of an assignment must b
The left-hand side of an assignment must be a variable这个怎么改?
“you must drive on the left-hand side of the road in Britain
In Hong Kong we drive on (the left-hand side) of the road.（对
go round the corner on your left-hand side
on the left side of the
word 设置 the left and right hand margis of your assignment sh
句型你必须靠马路左边行驶1You must drive on the left side of the road另一种句
on the left side
on the right-hand side of的中文意思是什么?
The traffic （ ） on the left side of the roa