作业帮亲们啊,谁帮我翻译一下这个,关于电路的?拜托了各位 谢谢
来源：学生作业帮 编辑：拍题作业网作业帮 分类：英语作业 时间：2024/04/25 10:26:21
亲们啊,谁帮我翻译一下这个,关于电路的?拜托了各位 谢谢
PROPOSED MULTIPLIER ARCHITECTURE A 16 bit signed (2’s complement) multiplier is designed using Wallace tree and modified booth algorithm as shown in Figure 4. The total number of partial products is reduced to half by using Booth encoding (Figure 3). This Booth encoder allows the correct multiplicand terms to feed into the partial product reduction tree. Partial product tree outputs fed into the 32 bit hybrid final adder completing a 16x16 bit multiplication operation. This organization of the multiplier is very suitable for 16 bit multiply operations which are essential in high performance low power embedded processors and DSP applications. The booth encoder and booth selector are realized by using the new differential MOS current mode gate circuits (Figure 5 and Figure 6).
PROPOSED MULTIPLIER ARCHITECTURE A 16 bit signed (2’s complement) multiplier is designed using Wallace tree and modified booth algorithm as shown in Figure 4. The total number of partial products is reduced to half by using Booth encoding (Figure 3). This Booth encoder allows the correct multiplicand terms to feed into the partial product reduction tree. Partial product tree outputs fed into the 32 bit hybrid final adder completing a 16x16 bit multiplication operation. This organization of the multiplier is very suitable for 16 bit multiply operations which are essential in high performance low power embedded processors and DSP applications. The booth encoder and booth selector are realized by using the new differential MOS current mode gate circuits (Figure 5 and Figure 6).
乘法器结构电路 16位有符号（2的补充）的乘法器是运用华勒斯树和改进的布斯算法来设计的,如图4所示.通过使用布斯编码,部分产品的总数被减少到一半（图3）.布斯编码器允许正确的乘数术语注入到部分产品约简树.部分产品树输出被注入最终32位混合加法器来完成16×16位乘法运算.这个乘数的机构非常适合于在高性能、低功耗嵌入式处理器和数字信号处理器的应用上必不可少的16位乘法运算.布斯编码器和布斯选择器是通过使用新的微分MOS电流模式门电路来实现的（图5和图6）.
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